Here is a good opportunity to learn more about Modern Code and to take some in depth training from Colfax. Please take a look!
http://colfaxresearch.com/how-15-10/
The 4th run of the Hands-On Workshop (HOW) on parallel programming begins October 13, 2015 with Session 1. All broadcasts start at 9 am Pacific daylight time. Information on connection to the Web-based training will be sent to you after registration. Attendees may receive a certificate of completion; attending at least 6 out of 10 sessions is required to receive the certificate from Colfax.
Live status as of 48 minutes ago: 169 registrants, 135 remote access seats requested. A total of 96 remote access seats will be made available. On wait list for remote access: 39 registrants.
http://colfaxresearch.com/how-15-10/
The 4th run of the Hands-On Workshop (HOW) on parallel programming begins October 13, 2015 with Session 1. All broadcasts start at 9 am Pacific daylight time. Information on connection to the Web-based training will be sent to you after registration. Attendees may receive a certificate of completion; attending at least 6 out of 10 sessions is required to receive the certificate from Colfax.
Live status as of 48 minutes ago: 169 registrants, 135 remote access seats requested. A total of 96 remote access seats will be made available. On wait list for remote access: 39 registrants.
Session 01 (Oct 13, 2015) – Hello World from Intel® Xeon Phi™ Coprocessors
In Session 1 we introduce Intel® Xeon® Processors and Intel® Xeon Phi™ Coprocessors and discuss their features and purpose. We also begin introduction to portable, future-proof parallel programming and discuss the pre-requisites for high performance on the Intel MIC architecture: thread parallelism, vectorization, and optimized memory access pattern. The episode introduces the native model for programming Intel Xeon Phi coprocessors that allows to re-use code of applications designed for general-purpose CPUs. The hands-on part of the episode demonstrates how the Linux operating system (OS) on the host inter-operates with the OS on coprocessors, and how to use Intel compilers to run native applications on coprocessors.
In Session 1 we introduce Intel® Xeon® Processors and Intel® Xeon Phi™ Coprocessors and discuss their features and purpose. We also begin introduction to portable, future-proof parallel programming and discuss the pre-requisites for high performance on the Intel MIC architecture: thread parallelism, vectorization, and optimized memory access pattern. The episode introduces the native model for programming Intel Xeon Phi coprocessors that allows to re-use code of applications designed for general-purpose CPUs. The hands-on part of the episode demonstrates how the Linux operating system (OS) on the host inter-operates with the OS on coprocessors, and how to use Intel compilers to run native applications on coprocessors.
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